Static Timing Analysis Engineer
Preferred at least 5+ years of Physical Design experience on high PHY and/or SOC designs
Deep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing STA constraints
Deep understanding of all aspects of Timing flow, Physical construction, Integration and Physical Verification
Confirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes
Experienced user of industry standard Timing, Physical Design and Synthesis tools
Deep Understanding of scripting languages such as Perl/Tcl
As a Timing Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on critical blocks by working with RTL, PD teams. Develop and validate high performance low power clock network guidelines. Perform Timing optimization and implement the design for functionality. Generate and Implement ECOs to fix timing etc. Run Timing verification flow at chip/block level and provide guidelines to fix violations to other designers and/or perform the fixes. Participate in establishing CAD and physical design methodologies for accurate by construction designs. Assist in flow development for chip integration.
Education & Experience
Bachelor or Master's degree in Electrical Engineering is required. Preferred at least 2 years of industry experience.
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